M. 1
15:00

MACROMODEL ESTABLISHED BY SIMU­LATIONS FOR THE ANALOG REGIME OF THE AVALANCHE GATE-CONTROLLED DIODE, A. Rusu, C. Ravariu, Alex. Rusu, D. Dobrescu, D. Cozma, “Politehnica” Univ. of Bucharest, Romania.

M. 2
15:20

SELF CONSISTENT PARAMETERIZED PHYSICAL MTJ COMPACT MODEL FOR STT-RAM, A. Nigam, K. Munira, A. Ghosh, S. Wolf, E. Chen*, M.R. Stan, Univ. of Virginia, *Grandis, Inc., USA.

M. 3
15:40

VERTICAL SCALING OF MULTI-STACK PLANAR GUNN DIODES, N.J. Pilgrim, A. Khalid*, C. Li*, G.M. Dunn, D.R.S. Cumming*, Univ. of Aberdeen, *Univ. of Glasgow, UK.

M. 4
16:00

POWER DISSIPATION CONSIDERATIONS IN LOW SIDE SWITCH DESIGN, A. Danchiv, M. Hulub, D. Manta, Infineon Technologies Romania, Bucharest, Romania.

M. 5
16:20

A SIMPLE METHOD TO IMPROVE THE ENERGY CAPABILITY OF LARGE DMOS POWER TRANSISTORS, D. Costachescu, M. Pfost, L. Goras*, Infineon Technologies Romania SCS, Bucharest, *“Gh. Asachi”, Technical Univ., Iasi, Romania.

M. 6
16:40

HOT SPOTS INDUCED BY REVERSE LEAKAGE CURRENT FLOW THROUGH THE SEMICONDUCTOR –DIELECTRIC INTERFACE FROM DEVICE PN JUNCTION PERIPHERY, V.V.N. Obreja, A.C. Obreja, K.I. Nuttall*, IMT–Bucharest, Romania, *The Liverpool Univ., UK.

M. 7
17:00

QUANTITATIVE ASSESSMENT OF THE SINGLE-BAND MODEL IN THE SILICON BASED RESONANT TUNNELLING DEVICES, T. Sandu, IMT–Bucharest, Romania.