Technology and performance of SiC-based Nanowire Field Effect Transistors
Konstantinos Zekentes
Theoretical studies on the 3C-SiC Nanowire Field Effect Transistors (NWFETs), in various transport regimes, have shown that the SiC NWFETs have similar performance to the Si-based ones while they offer, in addition, the advantage of high temperature operation and eventually efficient power dissipation for specific geometries.
The until-now demonstrated SiC-Nanowire Field Effect Transistors (NWFETs) have exhibited poor performance due to the high residual doping of the NWs as well as the bad interface with the gate dielectrics. Top-down NWs have been used for the SiC NWFETs fabrication on the basis of low-doped 3C-SiC material and eliminating, thus, the first reason. The transistors with top-down grown NWs exhibited three orders of magnitude higher current and transconductance values with respect to SiC NWFETs with bottom-up grown NWs. Nevertheless, it was not possible to switch-off the transistors showing the importance of interface with the gate dielectrics. Current effort is dedicated to improve the gate dielectric quality and fabricate Gate-All-Arround (GAA) transistors