Design and Modelling Challenges for Very Large Scale Integrated Quantum Processors in Foundry CMOS Technologies
by Sorin Voinigescu, Shai Bonen, Suyash Pati Tripathi, Lucy Wu, Apurv Bharadwaj, Thomas Jager, and Julie McIntosh
This presentation will discuss the main challenges in the physical implementation, design, hierarchical modelling and simulation of the scalable qubit array and of the cryogenic control and readout electronics for future Quantum Processors with millions of qubits manufactored in commercial FDSOI and FinFET foundry technologies. Impact of process manufacturing rules restrictions and process variation on qubit design and modelling, circuit heat dissipation and layout miniaturization to fit the qubit array pitch, qubit-to-qubit crosstalk, and the need for atomistic, classical, and behavioural qubit simulation and modelling will be covered in detail.