The project proposes to develop a new semiconductor ferroelectric at the wafer scale NiO:N (NiO doped with N) and based on it to develop switchable rectification devices, logic gates and transistors with memories where the logic operation and memory are in the same place. We have obtained the demonstration of the ferroelectricity in atomically-thin NiO doped with N. The advantages of a NiO:N ferroelectric semiconductor films are very important since on a single chip we can combine various functions of semiconductors, such as amplification and digital processing, with those specific of ferroelectrics, such as memory. Therefore, on a single chip, it could be possible to assemble all electronic functions for in-memory computing, going thus beyond the von Neumann computing architecture used today, in which the memory and the digital processing unit (ALU) are separated and the computer consumes the largest part of its electric power to transfer data between these two units.

The main outcome of this project will be the foundation of a technological platform for the ferroelectric field-effect-transistor memory devices, logic gates with memories, and for memory diodes devices with logic gates. First demonstrator (DM1) (designed to be realized from TRL 2 up to TRL 4) is a CMOS compatible device in which several layers are used forming an MFM (metal–ferroelectric–metal) diode in which, it is used, in first time, as a ferroelectric material, a NiO:N film, then with HfO2:Zr. The Ferroelectric films layer will have thicknesses between a few nanometers and 30 nm. Second demonstrator (DM2)(designed to be realized from TRL 2 up to TRL 4) is a ferroelectric FET (Fe-FET) having as channel a graphene monolayer transferred at the wafer scale.

Both demonstrators are advanced devices at the wafer scale in the area of neuromorphic computation since the logic and memory operations are taking in the same place as in the case of neurons.