The general objective of the project is to achieve ferroelectric field-effect transistor (FeFET) memories and logic gates based on ferroelectric diode memories used in future neuromorphic applications.
To accomplish the general objective of the project, the implementation plan was structured into three stages.

The first stage (Design of the manufacturing technology for the demonstrators, characterization of deposited ferroelectric thin films, and creation of the project website) comprised five activities and was dedicated to establishing the technical specifications of demonstrator 1 (DM1) and demonstrator 2 (DM2), obtaining and characterizing the first ferroelectric films (NiO:N and HfO2), designing the technological workflow of test structures based on ferroelectric films, and designing photolithographic masks. The objective set for the first stage - Growth and characterization of NiO:N ferroelectric films with different N doping levels at the wafer level was successfully achieved.
After preliminary studies on fabrication parameters and the establishment of the technological flow, preliminary models of the devices and two preliminary sets of photolithographic masks were obtained. Following complete morphological, structural, dielectric, and ferroelectric characterizations of the ultrafine NiO:N ferroelectric films and using different N doping concentrations grown by RF sputtering and Atomic Layer Deposition (ALD), preliminary synthesis procedures were obtained.

1. The basic geometric parameters of DM1 and DM2 were established after an in-depth study of the specialized literature.
2. The technological workflow for test structures based on ferroelectric films (NiO:N and HfO2) was designed, focusing on the optimal material parameters obtained. Within this activity, the corresponding set of photolithographic masks was designed and fabricated, and a risk assessment sheet based on the NPR risk index using the Failure Mode and Effects Analysis (FMEA) method was created.
3. The NiO:N and HfO2 films were deposited on conductive titanium nitride by RF reactive sputtering and by the ALD technique.
4. The ferroelectric films obtained by the end of the first stage were characterized morphologically (surface topography-AFM), structurally (X-ray diffraction-XRD, X-ray reflectometry-XRR), and their dielectric and ferroelectric properties were evaluated (polarization measurements).
5. The project website was initiated, containing general information about the project, its overall purpose, objectives, and obtained results.

The second stage (Deposition and characterization of ferroelectric thin films) comprised eight activities contained in three work packages and was dedicated to the deposition and characterization of ferroelectric films, analysis of deposition factors on ferroelectric properties, optimization of deposition parameters, as well as establishing the technical specifications of DM1 and DM2. The objective set for the second stage - Characterization of NiO ferroelectric thin films, was fully achieved.
After analyzing the data obtained from the characterization and investigation of factors influencing the characteristic ferroelectric films obtained, synthesis procedures and technical parameter sheets were optimized, thus establishing the technical specifications of DM1 and DM2.

 

1. Layers of ferroelectric films (NiO:N, HfO2:Zr, HfO2:Y, and HfO2) and oxides (NiO) were deposited;
2. To evaluate the properties of the ferroelectric materials used, as well as their relationships and influences, two types of devices were realized: ferroelectric storage capacitive structures (MIMIM) and ferroelectric field-effect structures (FeFET);
3. A thorough analysis of the influence of process parameters was conducted, establishing the optimal parameters for obtaining materials with the desired properties;
4. During the progress towards obtaining ferroelectric materials with the desired properties, the technical specifications for DM1 and DM2 were established;
5. For the Zr:HfO2/NiO:N/Ni/NiO:N/Zr:HfO2 heterostructures with HfZrO2 layer thicknesses of 7 nm, a sudden current jump was observed in the I-V curves, suggesting a strong reversible phase transition from an insulating state to a conductive state. The device can be used, after modeling according to requirements, as a switch in future logic circuits or as a short-term storage capacitive device;
6. Large memory window values were obtained on the NiO:N/Al2O3 device (MW=6.7V) and on the NiO/HfO:Y/Al2O3 device (MW=3.4V), allowing the storage of a broader spectrum of information or clearer distinction between different memory states;
7. Very good subthreshold slope values were obtained: SS = ∂VG/(logID) of 55 mV/decade in the steep region of the ID–VG characteristics for NiO:N/Al2O3 devices, and 61 mV for NiO/HfO/Al2O3 devices.
   
   

The third stage (Validation of TRL 3, TRL 4, and demonstration of the functionality of the demonstrators) comprised eight activities and focused on validating the technological functionality at TRL 3 and TRL 4 levels of the demonstrators. Objective 3, the validation of TRL 3, TRL 4, and the functionality of the demonstrators, was fully achieved.
Based on the data collected from WP1 and WP2, combined with the design and simulation results, an optimized scheme of the devices and manufacturing flows was produced, demonstrating the functionality of both demonstrators.
By correlating the project objectives with the current state of technology and the project results, it can be observed that the proposed objectives have been met and formulated in accordance with the current state of technology. Both demonstrator structures (DM1 and DM2) were fully fabricated and characterized at IMT-Bucharest and will make a significant contribution to a new family of logic gates based on MFM diodes and Fe-FET memories for future neuromorphic computing applications.

 

Technology Readiness Level (TRL) 

Estimated Results

Impact of the Results

Dissemination